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ISL9208
Data Sheet November 2, 2007 FN6446.1
Multi-Cell Li-ion Battery Pack OCP/Analog Front End
The ISL9208 is an overcurrent protection device and analog front end for a microcontroller in a multi-cell Li-ion battery pack. The ISL9208 supports battery pack configurations consisting of 5-cells to 7-cells in series and 1 or more cells in parallel. The ISL9208 provides integral overcurrent protection circuitry, short circuit protection, an internal 3.3V voltage regulator, internal cell balancing switches, cell voltage monitor level shifters, and drive circuitry for external FET devices for control of pack charge and discharge. Selectable overcurrent and short circuit thresholds reside in internal RAM registers. An external microcontroller sets the thresholds by setting register values through an I2C serial interface. Internal registers also contain the detection delays for overcurrent and short circuit conditions. Using an internal analog multiplexer the ISL9208 provides monitoring of each cell voltage plus internal and external temperature by a separate microcontroller with an A/D converter. Software on this microcontroller implements all battery pack control functionality, except for overcurrent and short circuit shutdown.
Features
* Software selectable overcurrent protection levels and variable protect detection times - 4 discharge overcurrent thresholds - 4 short circuit thresholds - 4 charge overcurrent thresholds - 8 overcurrent delay times (Charge) - 8 overcurrent delay times (Discharge) - 2 short circuit delay times (Discharge) * Automatic FET turn-off and cell balance disable on reaching external (battery) or internal (IC) temperature limit. * Automatic override of cell balance on reaching internal (IC) temperature limit. * Fast short circuit pack shutdown * Can use current sense resistor, FET rDS(ON), or Sense FET for overcurrent detection. * Four battery backed software controlled flags. * Allows three different FET controls: - Back-to-back N-Channel FETs for charge and discharge control - Single N-Channel discharge FET. - Single N-Channel FET for discharge, with separate, optional (smaller) back-to-back N-channel FETs for charge. * Integrated Charge/Discharge FET Drive Circuitry with 200A (typ) turn-on current and 150mA (typ) Discharge FET turn-off current. * 10% Accurate 3.3V voltage regulator (minimum 25mA out with external NPN transistor having current gain of 70). * Monitored cell voltage output stable in 100s. * Internal Cell balancing FETs handle up to 200mA of balancing current for each cell (with the number of cells being balanced limited by the maximum package power dissipation of 400mW).
Applications
* Power Tools * Battery Backup Systems * E-Bikes * Portable Test Equipment * Medical Systems * Hybrid Vehicle * Military Electronics
Ordering Information
PART NUMBER (Note) ISL9208IRZ* PART MARKING ISL9208 IRZ PACKAGE (Pb-free) 32 Ld 5x5 QFN PKG. DWG. # L32.5x5B
* Simple I2C host interface * Sleep operation with programmable negative edge or positive edge wake-up. * <10A Sleep Mode * Pb-free (RoHS compliant)
*Add "-T" suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL9208 Pinout
ISL9208 (32 LD QFN) TOP VIEW
TEMP3V WKUP RGC SDA RGO
NC VC7/VCC CB7 VCELL6 CB6 VCELL5 CB5 VCELL4
32 31 30 29 28 27 26 25 1 24 2 3 4 5 6 7 23 22 21 20 19 18
SCL
NC
NC
TEMPI AO VMON CFET DFET CSENSE DSENSE DSREF
8 17 9 10 11 12 13 14 15 16
CB4
CB3
CB2
CB1
VCELL3
VCELL2
Functional Diagram
SCL SDA
VCELL1
VSS I2C I/F 2
VC7/VCC CB7 VCELL6 CB6 VCELL5 CB5 VCELL4 CB4 VCELL3 CB3 VCELL2 CB2 VCELL1 CB1 BACKUP SUPPLY DSREF DSENSE VMON VSS CSENSE AO TEMPI TEMP3V LEVEL SHIFTERS/ CELL BALANCE CIRCUITS CELL VOLTAGES 7 MUX POWER CONTROL REGISTERS 3.3VDC REGULATOR CONTROL LOGIC OSC FET CONTROL CIRCUITRY TEMPERATURE SENSOR, INT/EXT COMPARATOR EXT TEMP ENABLE RGC RGO
WKUP
OVERCURRENT PROTECTION CIRCUITS (THRESHOLD DETECT AND TIMING)
DFET
2
CFET
FN6446.1 November 2, 2007
ISL9208 Pin Descriptions
SYMBOL VC7/VCC VCELLN CBN DESCRIPTION Battery cell 7 voltage input/VCC supply. This pin is used to monitor the voltage of this battery cell externally at pin AO. This pin also provides the operating voltage for the IC circuitry. Battery cell N voltage input. This pin is used to monitor the voltage of this battery cell externally at pin AO. VCELLN connects to the positive terminal of CELLN and the negative terminal of CELLN + 1. Cell balancing FET control output N. This internal FET diverts a fraction of the current around a cell while the cell is being charged or adds to the current pulled from a cell during discharge in order to perform a cell voltage balancing operation. This function is generally used to reduce the voltage on an individual cell relative to other cells in the pack. The cell balancing FETs are turned on or off by an external controller. Ground. This pin connects to the most negative terminal in the battery string. Discharge current sense reference. This input provides a separate reference point for the charge and discharge current monitoring circuits. WIth a separate reference connection, it is possible to minimize errors that result from voltage drops on the ground lead when the load is drawing large currents. If a separate reference is not necessary, connect this pin to VSS. Discharge current sense monitor. This input monitors the discharge current by monitoring a voltage. It can monitor the voltage across a sense resistor, or the voltage across the DFET, or by using a FET with a current sense pin. The voltage on this pin is measured with reference to DSREF. Charge current sense monitor. This input monitors the charge current by monitoring a voltage. It can monitor the voltage across a sense resistor, or the voltage across the CFET, or by using a FET with a current sense pin. The voltage on this pin is measured with reference to VSS. Discharge FET control. The ISL9208 controls the gate of a discharge FET through this pin. The power FET is a N-Channel device. The FET is turned on only by the microcontroller. The FET can be turned off by the microcontroller, but the ISL9208 also turns off the FET in the event of an overcurrent or short circuit condition. If the microcontroller detects an undervoltage condition on any of the battery cells, it can turn off the discharge FET by controlling this output with a control bit. Charge FET control. The ISL9208 controls the gate of a charge FET through this pin. The power FET is a N-Channel device. The FET is turned on only by the microcontroller. The FET can be turned off by the microcontroller, but the ISL9208 also turns off the FET in the event of an overcurrent condition. If the microcontroller detects an overvoltage condition on any of the battery cells, it can turn off the FET by controlling this output with a control bit. Discharge load monitoring. In the event of an overcurrent or short circuit condition, the microcontroller can enable an internal resistor that connects between the VMON pin and VSS. When the FETs open because of an overcurrent or short circuit condition and the load remains, the voltage at VMON will be near the VCC voltage. When the load is released, the voltage at VMON drops below a threshold indicating that the overcurrent or short circuit condition is resolved. At this point, the LDFAIL flag is cleared and operation can resume. Analog multiplexer output. The analog output pin is used by an external microcontroller to monitor the cell voltages and temperature sensor voltages. The microcontroller selects the specific voltage being applied to the output by writing to a control register. Temperature monitor output control. This pin outputs a voltage to be used in a divider that consists of a fixed resistor and a thermistor. The thermistor is located in close proximity to the cells. The TEMP3V output is connected internally to the RGO voltage through a PMOS switch only during a measurement of the temperature, otherwise the TEMP3V output is off. The TEMP3V output can be turned on continuously with a special control bit. Microcontroller wake up control. The TEMP3V pin is also turned on when any of the DSC, DOC, or COC bits are set. This can be used to wake up a sleeping microcontroller to respond to overcurrent conditions with its own control mechanism. Temperature monitor input. This pin inputs the voltage across a thermistor to determine the temperature of the cells. When this input drops below TEMP3V/13, an external over-temperature condition exists. The TEMPI voltage is also fed to the AO output pin through an analog multiplexer so the temperature of the cells can be monitored by the microcontroller. Regulated output voltage. This pin connects to the emitter of an external NPN transistor and works in conjunction with the RGC pin to provides a regulated 3.3V. The voltage at this pin provides feedback for the regulator and power for many of the ISL9208 internal circuits as well as providing the 3.3V output voltage for the microcontroller and other external circuits. Regulated output control. This pin connects to the base of an external NPN transistor and works in conjunction with the RGO pin to provide a regulated 3.3V. The RGC output provides the control signal for the external transistor to provide the 3.3V regulated voltage on the RGO pin. Wake up Voltage. This input wakes up the part when the voltage crosses a turn-on threshold (wake up is edge triggered). The condition of the pin is reflected in the WKUP bit (The WKUP bit is level sensitive.) WKPOL bit = "1": the device wakes up on the rising edge of the WKUP pin. Also, the WKUP bit is HIGH only when the WKUP pin voltage > threshold. WKPOL bit = "0", the device wakes up on the falling edge of the WKUP pin. Also, the WKUP bit is HIGH only when the WKUP pin voltage < threshold. Serial Data. This is the bidirectional data line for an I2C interface. Serial Clock. This is the clock input for an I2C communication link.
VSS DSREF
DSENSE
CSENSE
DFET
CFET
VMON
AO TEMP3V
TEMPI
RGO
RGC
WKUP
SDA SCL
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FN6446.1 November 2, 2007
ISL9208
Absolute Maximum Ratings
Power Supply Voltage, VCC . . . . . . . . . .VSS - 0.5V to VSS + 36.0V Cell voltage, VCELL VCELLN - (VCELLN-1), VCELL1-VSS . . . . . . . . . . . . . -0.5V to 5V Terminal Voltage, VTERM1 (SCL, SDA, CSENSE, DSENSE, TEMPI, RGO, AO, TEMP3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS - 0.5 to VRGO + 0.5V Terminal Voltage, VTERM2 (CFET, VMON) . . . . VSS - 22.0V to VCC Terminal Voltage, VTERM3 (WKUP) . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS - 0.5V to VCC (VCC <27V) Terminal Voltage, VTERM4 (RGC) . . . . . . . . . . . . . VSS - 0.5V to 5V Terminal Voltage, VTERM5, (all other pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS - 0.5V to VCC + 0.5V
Thermal Information
Thermal Resistance (Typical, Notes 1, 2) JA (C/W) JC (C/W) 32 Ld QFN . . . . . . . . . . . . . . . . . . . . . . 32 2 Continuous Package Power Dissipation . . . . . . . . . . . . . . . . .400mW Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to +125C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . . 5V to 10V Operating Voltage: VCC pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2V to 30.1V VCELL1-VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3V to 4.3V VCELLN-(VCELLN-1). . . . . . . . . . . . . . . . . . . . . . . . . 2.3V to 4.3V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 2. JC, "case temperature" location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Operating Specifications Over the recommended operating conditions unless otherwise specified.
PARAMETER Operating Voltage Power-Up Condition 1 Power-Up Condition 2 Threshold SYMBOL VCC VPORVCC VCC voltage (Note 3) VPOR123 VCELL1 - VSS and VCELL2 - VCELL1 and VCELL3 - VCELL2 (rising) (Note 3) VPORhys VCELL1 - VSS and VCELL2 - VCELL1 and VCELL3 - VCELL2 (falling) (Note 3) VRGO IRGC IVCC1 IRGO1 IVCC2 0A < IRGC < 350A (Control current at output of RGC. Recommend NPN with gain of 70+) Power-up defaults, WKUP pin = 0V. Power-up defaults, WKUP pin = 0V. LDMONEN bit = 1, VMON floating, CFET = 1, DFET=1, WKPOL bit = 1, VWKUP = 10V, [AO3:AO0] bits = 03H. LDMONEN bit = 1, VMON floating, CFET = 1, DFET=1, WKPOL bit = 1, VWKUP = 10V, [AO3:AO0] bits = 03H. Default register settings, except SLEEP bit = 1. WKUP pin = VCELL1 Default register settings, except SLEEP bit = 1. WKUP pin = VCELL1 AO3:AO0 bits = 0000H 3.0 0.35 1.1 TEST CONDITION MIN 9.2 4 1.7 TYP MAX 30.1 9.2 2.3 UNIT V V V
Power-Up Condition 2 Hysteresis
70
mV
3.3V Regulated Voltage 3.3VDC Voltage Regulator Control Current Limit VCC Supply Current RGO Supply Current VCC Supply Current
3.3 0.50 400 300 500
3.6
V mA
510 410 700
A A A
RGO Supply Current
IRGO2
450
650
A
VCC Supply Current RGO Supply Current VCELL Input Current (VCELL1)
IVCC3 IRGO3 IVCELL1
10 1 14
A A A
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FN6446.1 November 2, 2007
ISL9208
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
PARAMETER VCELL Input Current (VCELLN) SYMBOL TEST CONDITION MIN TYP MAX 10 UNIT A IVCELLN AO3:AO0 bits = 0000H
OVERCURRENT/SHORT CIRCUIT PROTECTION SPECIFICATIONS Overcurrent Detection Threshold (Discharge) Voltage Relative To DSREF (Default in Boldface) VOCD VOCD = 0.10V (OCDV1, OCDV0 = 0, 0) VOCD = 0.12V (OCDV1, OCDV0 = 0,1) VOCD = 0.14V (OCDV1, OCDV0 = 1,0) VOCD = 0.16V (OCDV1, OCDV0 = 1,1) Overcurrent Detection Threshold (Charge) Voltage Relative to DSREF (Default in Boldface) VOCC VOCC = 0.10V (OCCV1, OCCV0 = 0, 0) VOCC = 0.12V (OCCV1, OCCV0 = 0,1) VOCC = 0.14V (OCCV1, OCCV0 = 1,0) VOCC = 0.16V (OCCV1, OCCV0 = 1,1) Short Current Detection Threshold Voltage Relative to DSREF (Default in Boldface) VSC VOC = 0.20V (SCDV1, SCDV0 = 0, 0) VOC = 0.35V (SCDV1, SCDV0 = 0,1) VOC = 0.65V (SCDV1, SCDV0 = 1, 0) VOC = 1.20V (SCDV1, SCDV0 = 1,1) Load Monitor Input Threshold (Falling Edge) Load Monitor Input Threshold (Hysteresis) Load Monitor Current Short Circuit Time-out VVMON LDMONEN bit = "1" 0.08 0.10 0.12 0.14 -0.12 -0.14 -0.16 -0.18 0.15 0.30 0.60 1.10 1.1 0.10 0.12 0.14 0.16 -0.10 -0.12 -0.14 -0.16 0.20 0.35 0.65 1.20 1.45 0.25 20 Short circuit detection delay (SCLONG bit = `0') Short circuit detection delay (SCLONG bit = `1') Over Discharge Current Time-out (Default In Boldface) tOCD tOCD = 160ms (OCDT1, OCDT0 = 0, 0 and DTDIV = 0) tOCD = 320ms (OCDT1, OCDT0 = 0, 1 and DTDIV = 0) tOCD = 640ms (OCDT1, OCDT0 = 1, 0 and DTDIV = 0) tOCD = 1280ms (OCDT1, OCDT0 = 1, 1 and DTDIV = 0) tOCD = 2.5ms (OCDT1, OCDT0 = 0, 0 and DTDIV = 1) tOCD = 5ms (OCDT1, OCDT0 = 0, 1 and DTDIV = 1) tOCD = 10ms (OCDT1, OCDT0 = 1, 0 and DTDIV = 1) tOCD = 20ms (OCDT1, OCDT0 = 1, 1 and DTDIV = 1) 90 5 80 160 320 640 1.25 2.5 5 10 40 190 10 160 320 640 1280 2.50 5 10 20 60 290 15 240 480 960 1920 3.75 7.5 15 30 0.12 0.14 0.16 0.18 -0.07 -0.09 -0.11 -0.13 0.25 0.40 0.70 1.30 1.8 V V V V V V V V V V V V V mV A s ms ms ms ms ms ms ms ms ms
VVMONH LDMONEN bit = "1" IVMON tSCD
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FN6446.1 November 2, 2007
ISL9208
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
PARAMETER Over Charge Current Time-out (Default In Boldface) SYMBOL tOCC TEST CONDITION tOCC = 80ms (OCCT1,OCCT0 = 0, 0 and CTDIV = 0) tOCC = 160ms (OCCT1, OCCT0 = 0, 1 and CTDIV = 0) tOCC = 320ms (OCCT1, OCCT0 = 1, 0 and CTDIV = 0) tOCC = 640ms (OCCT1, OCCT0 = 1, 1 and CTDIV = 0) tOCC = 2.5ms (OCCT1, OCCT0 = 0, 0 and CTDIV = 1) tOCC = 5ms (OCCT1, OCCT0 = 0, 1 and CTDIV = 1) tOCC = 10ms (OCCT1, OCCT0 = 1, 0 and CTDIV = 1) tOCC = 20ms (OCCT1, OCCT0 = 1, 1 and CTDIV = 1) OVER-TEMPERATURE PROTECTION SPECIFICATIONS Internal Temperature Shutdown Threshold Internal Temperature Hysteresis TINTSD THYS Temperature drop needed to restore operation after over-temperature shutdown. 125 20 C C MIN 40 80 160 320 1.25 2.5 5 10 TYP 80 160 320 640 2.50 5 10 20 MAX 120 240 480 960 3.75 7.5 15 30 UNIT ms ms ms ms ms ms ms ms
Internal Over-temperature Turn On Delay Time External Temperature Output Current External Temperature Limit Threshold
tITD IXT TXTF Current output capability at TEMP3V pin Voltage at VTEMPI; Relative to falling edge V TEMP3V
-----------------------------
128 1.2 -20 0 +20
ms mA mV
13
External Temperature Limit Hysteresis External Temperature Monitor Delay
TXTH tXTD
Voltage at VTEMPI. Delay between activating the external sensor and the internal over-temperature detection. TEMP3V is ON (3.3V)
60
110 1
160
mV ms
External Temperature Autoscan On Time External Temperature Autoscan Off Time
tXTAON
5 635
ms ms
tXTAOFF TEMP3V output is off.
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FN6446.1 November 2, 2007
ISL9208
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
PARAMETER ANALOG OUTPUT SPECIFICATIONS Cell Monitor Analog Output Voltage Accuracy Cell Monitor Analog Output External Temperature Accuracy VAOC VAOXT [VCELLN - (VCELLN-1)]/2 - AO External temperature monitoring accuracy. Voltage error at AO when monitoring TEMPI voltage (measured with TEMPI = 1V) -15 -10 4 30 10 mV mV SYMBOL TEST CONDITION MIN TYP MAX UNIT
Internal Temperature Monitor Output Voltage Slope Internal Temperature Monitor Output AO Output Stabilization Time
VINTMON Internal temperature monitor voltage change TINT25 tVSC Output at +25C From SCL falling edge at data bit 0 of command to AO output stable within 0.5% of final value. AO voltage steps from 0V to 2V. (CAO = 10pF) (Note 7)
-3.5 1.31 0.1
mV/C V ms
CELL BALANCE SPECIFICATIONS Cell Balance Transistor rDS(ON) Cell Balance Transistor Current WAKE UP/SLEEP SPECIFICATIONS Device WKUP Pin Voltage Threshold VWKUP1 WKUP pin rising edge (WKPOL = 1) (WKUP Pin Active High - Rising Edge) Device wakes up and sets WKUP flag HIGH. Device Wkup Pin Hysteresis (WKUP Pin Active High) Input Resistance On WKUP Device WKUP Pin Active Voltage Threshold (WKUP Pin Active Low Falling Edge) Device Wkup Pin Hysteresis (WKUP Pin Active Low) Device Wake-up Delay VWKUP1H WKUP pin falling edge hystersis (WKPOL = 1) sets WKUP flag LOW (does not automatically enter sleep mode) RWKUP Resistance from WKUP pin to VSS (WKPOL = 1) 130 VCELL1 - 2.6 3.5 5.0 6.5 V RCB ICB (Note 6) 5 200 mA
100
mV
230
330
k V
VWKUP2 WKUP pin falling edge (WKPOL = 0) Device wakes up and sets WKUP flag HIGH. VWKUP2H WKUP pin rising edge hysteresis (WKPOL = 0) sets WKUP flag LOW (does not automatically enter sleep mode) tWKUP Delay after voltage on WKUP pin crosses the threshold (rising or falling) before activating the WKUP bit.
VCELL1 - 2.0 VCELL1 - 1.2
200
mV
20
40
60
ms
FET CONTROL SPECIFICATIONS (FOR VCELL1, VCELL2, VCELL3 VOLTAGES FROM 2.8V TO 4.3V) Control Outputs Response Time (CFET, DFET) CFET Gate Voltage DFETGate Voltage FET Turn On Current (DFET) FET Turn On Current (CFET) FET Turn Off Current (DFET) DFET Resistance to VSS tCO VCFET VDFET IDFON ICF(ON) Bit 0 to start of control signal (DFET) Bit 1 to start of control signal (CFET) No load on CFET No load on DFET DFET voltage = 0 to VCELL3 -1.5V CFET voltage = 0 to VCELL3 - 1.5V VCELL3 - 0.5 VCELL3 - 0.5 80 80 100 130 200 180 11 1.0 VCELL3 VCELL3 400 400 s V V A A mA
IDF(OFF) DFET voltage = VDFET to 1V RDF(OFF) VDFET <1V (When turning off the FET)
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FN6446.1 November 2, 2007
ISL9208
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT SERIAL INTERFACE CHARACTERISTICS SCL Clock Frequency Pulse Width Suppression Time at SDA and SCL Inputs SCL Falling Edge to SDA Output Data Valid Time the Bus Must Be Free Before Start of New Transmission Clock Low Time Clock High Time Start Condition Setup Time Start Condition Hold Time Input Data Setup Time fSCL tIN tAA Any pulse narrower than the max spec is suppressed. From SCL falling crossing VIH(min), until SDA exits the VIL(max) to VIH(min) window. SDA crossing VIH(min) during a STOP condition to SDA crossing VIH(min) during the following START condition. Measured at the VIL(max) crossing. Measured at the VIH(min) crossing. SCL rising edge to SDA falling edge. Both crossing the VIH(min) level. From SDA falling edge crossing VIL(max) to SCL falling edge crossing VIH(min). From SDA exiting the VIL(max) to VIH(min) window to SCL rising edge crossing VIL(min). From SCL falling edge crossing VIH(min) to SDA entering the VIL(max) to VIH(min) window. From SCL rising edge crossing VIH(min) to SDA rising edge crossing VIL(max). 4.7 100 50 3.5 kHz ns s
tBUF
s
tLOW tHIGH tSU:STA tHD:STA tSU:DAT
4.7 4.0 4.7 4.0 250
s s s s ns
Input Data Hold Time
tHD:DAT
300
s
Stop Condition Setup Time Stop Condition Hold Time Data Output Hold Time
tSU:STO
4.0 4.0 0
s s ns
tHD:STO From SDA rising edge to SCL falling edge. Both crossing VIH(min). tDH From SCL falling edge crossing VIL(max) until SDA enters the VIL(max) to VIH(min) window. (Note 4) From VIL(max) to VIH(min). From VIH(min) to VIL(max). Total on-chip and off-chip Maximum is determined by tR and tF. For CB = 400pF, max is about 2k ~ 2.5k For CB = 40pF, max is about 15k to 20k
SDA and SCL Rise Time SDA and SCL Fall Time Capacitive Loading Of SDA Or SCL SDA and SCL Bus Pull-up ResistorOff Chip Input Leakage Current (SCL, SDA) Input Buffer Low Voltage (SCL, SDA) Input Buffer High Voltage (SCL, SDA) Output Buffer Low Voltage (SDA)
tR tF Cb ROUT
1000 300 400 1
ns ns pF k
ILI VIL VIH VOL Voltage relative to VSS of the device. Voltage relative to VSS of the device. IOL = 1mA
-10 -0.3 VRGO x 0.7
10 VRGO x 0.3 VRGO + 0.1 V 0.4
A V V V V
SDA and SCL Input Buffer Hysteresis I2CHYST Sleep bit = 0 NOTES:
0.05 * VRGO
3. Power up of the device requires all VCELL1, VCELL2, VCELL3, and VCC to be above the limits specified. 4. The device provides an internal hold time of at least 300ns for the SDA signal to bridge the unidentified region of the falling edge of SCL. 5. Typical +125C 10%, based on design and characterization data. 6. Typical 5 2, based on design and characterization data. 7. Maximum output capacitance = 15pF.
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FN6446.1 November 2, 2007
ISL9208 Wake up timing (WKPOL = 0)
WKUP PIN
VWKUP2H WKUP BIT
Wake up timing (WKPOL = 1)
WKUP PIN
VWKUP1H WKUP BIT
Change in Voltage Source, FET Control
SCL BIT 3 BIT 2 BIT 1 DATA BIT 0 BIT 1 BIT 0
SDA
AO tVSC tVSC
tCO DFET
tCO
tCO
CFET
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FN6446.1 November 2, 2007
ISL9208 Automatic Temperature Scan
AUTO TEMP CONTROL (INTERNAL ACTIVATION) MONITOR TIME = 5ms 3.3V TEMP3V PIN EXTERNAL TEMPERATURE OVER-TEMPERATURE THRESHOLD 635ms HIGH IMPEDANCE
TMP3V/13
DELAY TIME = 1ms
DELAY TIME = 1ms MONITOR TEMP DURING THIS TIME PERIOD
XOT BIT FET SHUTDOWN AND CELL BALANCE TURN OFF (IF ENABLED)
Discharge Overcurrent/Short Circuit Monitor (Assumes DENOCD and DENSCD bits are `0')
VSC
VOCD VDSENSE tSCD `0' `0' 3.3V TEMP3V OUTPUT REGISTER 1 READ VCELL3 DFET OUTPUT UC TURNS ON DFET REGISTER 1 READ tOCD `1' `1' tSCD
DOC BIT DSC BIT
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FN6446.1 November 2, 2007
ISL9208 Charge Overcurrent Monitor (Assumes DENOCC bit is `0')
VCSENSE VOCC
tOCC `0' 3.3V TEMP3V OUTPUT REGISTER 1 READ 12V CFET OUTPUT C TURNS ON CFET `1'
COC BIT
Serial Interface Timing Diagrams
Bus Timing
tF tHIGH tLOW tR
SCL tSU:STA tHD:STA SDA (INPUT TIMING) tSU:DAT
tHD:DAT
tSU:STO
tAA SDA (OUTPUT TIMING)
tDH
tBUF
Symbol Table
WAVEFORM INPUTS MUST BE STEADY MAY CHANGE FROM LOW TO HIGH MAY CHANGE FROM HIGH TO LOW OUTPUTS WILL BE STEADY WILL CHANGE FROM LOW TO HIGH WILL CHANGE FROM HIGH TO LOW WAVEFORM INPUTS DON'T CARE: CHANGES ALLOWED N/A OUTPUTS CHANGING: STATE NOT KNOWN CENTER LINE IS HIGH IMPEDANCE
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FN6446.1 November 2, 2007
ISL9208 Registers
TABLE 1. REGISTERS ADDR 00H REGISTER Config/Op Status Operating Status
(Note 10)
READ/WRITE Read only
7 Reserved
6 Reserved
5 SA Single AFE XOT Ext over temp CB5ON
4 WKUP WKUP pin Status IOT Int over Temp CB4ON
3 Reserved
2 Reserved
1 Reserved
0 Reserved
01H
Read only
Reserved
Reserved
LDFAIL Load Fail (VMON) CB3ON
DSC Short Circuit CB2ON
COC DOC Discharge Charge OC OC CB1ON Reserved
02H
Cell Balance
Read/Write
CB7ON
CB6ON
Cell balance FET control bits 03H Analog Out Read/Write UFLG1 UFLG0 User Flag 1 User Flag 0 SLEEP Force Sleep (Note 11) DENOCD Turn off automatic OCD control DENOCC Turn off automatic OCC control LDMONEN Turn on VMON connection OCDV1 Reserved Reserved AO3 AO2 AO1 AO0
Analog output select bits Reserved Reserved Reserved Reserved CFET Turn on Charge FET (Note 12) OCDT1 DFET Turn on Discharge FET (Note 12) OCDT0
04H
FET Control
Read/Write
05H
Discharge Set
Read/Write (Write only if DISSETEN bit set)
OCDV0
DENSCD
SCDV1
SCDV0
Overcurrent Discharge Threshold Voltage
Short Circuit Discharge Turn off Threshold Voltage automatic SCD control SCLONG Long Shortcircuit delay CTDIV Divide charge time by 32 DTDIV Divide discharge time by 64
Overcurrent Discharge Time-out
06H
Charge Set
Read/Write (Write only if CHSETEN bit set)
OCCV1
OCCV0
OCCT1
OCCT0
Overcurrent Charge Threshold Voltage
Overcurrent Charge Time-out
07H
Feature Set
Read/Write (Write only if FSETEN bit set)
DIS3 ATMPOFF Turn off Disable 3.3V automatic reg. (device external requires temp scan external 3.3V) FSETEN Enable Feature Set writes
TMP3ON Turn on Temp3V
DISXTSD Disable external thermal shutdown
DISITSD Disable internal thermal shutdown
POR DISWKUP Force POR Disable WKUP pin
WKPOL Wake Up Polarity
08H
Write Enable
Read/Write
UFLG3 UFLG2 Reserved CHSETEN DISSETEN User Flag 3 User Flag 2 Enable Enable Charge Set Discharge Set writes writes RESERVED
Reserved
Reserved
09H:FFH NOTES:
Reserved
NA
8. A "1" written to a control or configuration bit causes the action to be taken. A "1" read from a status bit indicates that the condition exists. 9. "Reserved" indicates that the bit or register is reserved for future expansion. When writing to addresses 2, 3, 4, and 8: write a reserved bit with the value "0". Do not write to reserved registers at addresses 09H through FFH. Ignore reserved bits that are returned in a read operation. 10. These status bits are automatically cleared when the register is read. All other status bits are cleared when the condition is cleared. 11. This SLEEP bit is cleared on initial power up, by the WKUP pin going high (when WKPOL = "1") or by the WKUP pin going low (when WKPOL = "0"), and by writing a "0" to the location with an I2C command. 12. When the automatic responses are enabled, these bits are automatically reset by hardware when an overcurrent or short circuit condition turns off the FETs. At all other times, an I2C write operation controls the output to the respective FET and a read returns the current state of the FET drive output circuit (though not the actual voltage at the output pin.)
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FN6446.1 November 2, 2007
ISL9208 Status Registers
TABLE 2. CONFIG/OP STATUS REGISTER (ADDR: 00H) BIT 7 6 5 4 FUNCTION RESERVED RESERVED SA Single AFE Reserved for future expansion. Reserved for future expansion. Indicates the device is an ISL9208. This bit is set in the chip and cannot be changed. DESCRIPTION
WKUP This bit is set and reset by hardware. Wakeup pin status When `WKPOL' is HIGH: 'WKUP' HIGH = WKUP pin > Threshold voltage `WKUP' LOW = WKUP pin < Threshold voltage When `WKPOL' is LOW: 'WKUP' HIGH = WKUP pin < Threshold voltage `WKUP' LOW = WKUP pin > Threshold voltage RESERVED RESERVED RESERVED RESERVED Reserved for future expansion. Reserved for future expansion. Reserved for future expansion. Reserved for future expansion.
3 2 1 0
TABLE 3. OPERATING STATUS REGISTER (ADDR: 01H) BIT 7 6 5 4 3 FUNCTION RESERVED RESERVED XOT Ext Over-temp IOT Int Over-temp Reserved for future expansion. Reserved for future expansion. This bit is set to "1" when the external thermistor indicates an over-temperature condition. If the temperature condition has cleared, this bit is reset when the register is read. This bit is set to "1" when the internal thermistor indicates an over-temperature condition. If the temperature condition has cleared, this bit is reset when the register is read. DESCRIPTION
LDFAIL When the function is enabled, this bit is set to "1" by hardware when a discharge overcurrent or short circuit condition Load Fail (VMON) occurs and the load remains heavy. When the load fail condition is cleared or under a light load, the bit is reset when the register is read. DSC Short Circuit DOC Discharge OC COC Charge OC This bit is set by hardware when a short circuit condition occurs during discharge. When the discharge short circuit condition is removed, the bit is reset when the register is read. This bit is set by hardware when an overcurrent condition occurs during discharge. When the discharge overcurrent condition is removed, the bit is reset when the register is read. This bit is set by hardware when an overcurrent condition occurs during charge. When the charge overcurrent condition is removed, the bit is reset when the register is read.
2 1 0
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ISL9208 Control Registers
TABLE 4. CELL BALANCE CONTROL REGISTER (ADDR: 02H) CONTROL REGISTER BITS BIT 7 CB7ON x x x x x x x x x x x x 1 0 Bit 0 BIT 6 CB6ON x x x x x x x x x x 1 0 x x RESERVED BIT 5 CB5ON x x x x x x x x 1 0 x x x x BIT 4 CB4ON x x x x x x 1 0 x x x x x x BIT 3 CB3ON x x x x 1 0 x x x x x x x x BIT 2 CB2ON x x 1 0 x x x x x x x x x x BIT 1 CB1ON 1 0 x x x x x x x x x x x x BALANCE Cell1 ON Cell1 OFF Cell2 ON Cell2 OFF Cell3 ON Cell3 OFF Cell4 ON Cell4 OFF Cell5 ON Cell5 OFF Cell6 ON Cell6 OFF Cell7 ON Cell7 OFF
Reserved for future expansion TABLE 5. ANALOG OUT CONTROL REGISTER (ADDR: 03H)
BITS 7 6 5:4 BIT 3 AO3 0 0 0 0 0 0 0 0 1 1 1 1 BIT 2 AO2 0 0 0 0 1 1 1 1 0 0 x 1
FUNCTION UFLG1 User Flag 1 UFLG0 User Flag 0 RESERVED BIT 1 AO1 0 0 1 1 0 0 1 1 0 0 1 x
DESCRIPTION General purpose flag usable by microcontroller software. This bit is battery backed up, even when RGO turns off. General purpose flag usable by microcontroller software. This bit is battery backed up, even when RGO turns off. Reserved for future expansion BIT 0 AO0 0 1 0 1 0 1 0 1 0 1 x x OUTPUT VOLTAGE No Output (low power state) VCELL1 VCELL2 VCELL3 VCELL4 VCELL5 VCELL6 VCELL7 External Temperature Internal Temperature RESERVED RESERVED
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FN6446.1 November 2, 2007
ISL9208 Configuration Registers
The device is configured for specific application requirements using the Configuration Registers. The configuration registers consist of SRAM memory. This memory is powered by the RGO output. In a sleep condition, an internal switch converts power for the contents of these registers from RGO to the VCELL1 input.
TABLE 6. FET CONTROL REGISTER (ADDR: 04H) BIT 7 FUNCTION SLEEP Force Sleep DESCRIPTION Setting this bit to "1" forces the device to go into a sleep condition. This turns off both FET outputs, the cell balance outputs and the voltage regulator. This also resets the CFET, DFET, and CB7ON:CB1ON bits. The SLEEP bit is automatically reset to "0" when the device wakes up. This bit does not reset the AO3:AO0 bits. Writing a "1" to this bit turns on the VMON circuit. Writing a "0" to this bit turns off the VMON circuit. As such, the microcontroller has full control of the operation of this circuit. Reserved for future expansion. Setting this bit to "1" turns on the charge FET. Setting this bit to "0" turns off the charge FET. This bit is automatically reset in the event of a charge overcurrent condition, unless the automatic response is disabled by the DENOCC bit. Setting this bit to "1" turns on the discharge FET. Setting this bit to "0" turns off the discharge FET. This bit is automatically reset in the event of a discharge overcurrent or discharge short circuit condition, unless the automatic response is disabled by the DENOCD or DENSCD bits.
6 5:2 1
LDMONEN Turn on VMON connection RESERVED CFET
0
DFET
TABLE 7. DISCHARGE SET CONFIG REGISTER (ADDR: 05H) SETTING Bit 7 DENOCD Turn off automatic OC discharge control BIT 5 OCDV0 0 1 0 1 DENSCD Turn off automatic SC discharge control BIT 2 SCDV0 0 1 0 1 BIT 0 OCDT0 0 1 0 1 VSCD = 0.20V VSCD = 0.35V VSCD = 0.65V VSCD = 1.20V OVERCURRENT DISCHARGE TIME-OUT tOCD = 160ms (2.5ms if DTDIV = 1) tOCD = 320ms (5ms if DTDIV = 1) tOCD = 640ms (10ms if DTDIV = 1) tOCD = 1280ms (20ms if DTDIV = 1) VOCD = 0.10V VOCD = 0.12V VOCD = 0.14V VOCD = 0.16V When set to `0', a discharge short circuit condition turns off the FETs. When set to `1', a discharge short circuit condition will not automatically turn off the FETs. In either case, the condition sets the SCD bit, which also turns on the TEMP3V output. SHORT CIRCUIT DISCHARGE VOLTAGE THRESHOLD FUNCTION When set to `0', a discharge overcurrent condition automatically turns off the FETs. When set to `1', a discharge overcurrent condition will not automatically turn off the FETs. In either case, this condition sets the DOC bit, which also turns on the TEMP3V output. OVERCURRENT DISCHARGE VOLTAGE THRESHOLD
BIT 6 OCDV1 0 0 1 1 Bit 4
BIT 3 SCDV1 0 0 1 1 BIT 1 OCDT1 0 0 1 1
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ISL9208
TABLE 8. CHARGE/TIME SCALE CONFIG REGISTER (ADDR: 06H) SETTING Bit 7 DENOCC Turn off automatic OC charge control BIT 5 OCCV0 0 1 0 1 SCLONG Short circuit long delay CTDIV Divide charge time by 32 DTDIV Divide discharge time by 64 BIT 0 OCCT0 0 1 0 1 VOCD = 0.10V VOCD = 0.12V VOCD = 0.14V VOCD = 0.16V When this bit is set to `0', a short circuit needs to be in effect for 190us before a shutdown begins. When this bit is set to `1', a short circuit needs to be in effect for 10ms before a shutdown begins. When set to "1", the charge overcurrent delay time is divided by 32. When set to "0", the charge overcurrent delay time is divided by 1. When set to "1", the discharge overcurrent delay time is divided by 64. When set to "0", the discharge overcurrent delay time is divided by 1. OVERCURRENT CHARGE TIME-OUT tOCC = 80ms (2.5ms if CTDIV=1) tOCC = 160ms (5ms if CTDIV=1) tOCC = 320ms (10ms if CTDIV=1) tOCC = 640ms (20ms if CTDIV=1) FUNCTION When set to `0', a charge overcurrent condition automatically turns off the FETs. When set to `1', a charge overcurrent condition will not automatically turn off the FETs. In either case, this condition sets the COC bit, which also turns on the TEMP3V output. OVERCURRENT CHARGE VOLTAGE THRESHOLD
BIT 6 OCCV1 0 0 1 1 Bit 4
Bit 3 Bit 2 BIT 1 OCCT1 0 0 1 1
TABLE 9. FEATURE SET CONFIGURATION REGISTER (ADDR: 07H) BIT 7 6 5 4 FUNCTION DESCRIPTION
ATMPOFF When set to `1' this bit disables the automatic temperature scan. When set to `0', the temperature Turn off automatic external temp scan is turned on for 5ms in every 640ms. DIS3 Disable 3.3V reg TMP3ON Turn on Temp 3.3V DISXTSD Disable external thermal shutdown DISITSD Disable internal thermal shutdown POR Force POR DISWKUP Disable WKUP pin Setting this bit to "1" disables the internal 3.3V regulator. Setting this bit to "1" requires that there be an external 3.3V regulator connected to the RGO pin. Setting this bit to "1" turns ON the TEMP3V output to the external temperature sensor. The output will remain on as long as this bit remains "1". Setting this bit to "1" disables the automatic shutdown of the cell balance and power FETs in response to an external over-temperature condition. While the automatic response is disabled, the XOT flag is set so the microcontroller can initiate a shutdown based on the XOT flag. Setting this bit to "1" disables the automatic shutdown of the cell balance and power FETs in response to an internal over-temperature condition. While the automatic response is disabled, the IOT flag is set so the microcontroller can initiate a shutdown based on the IOT flag. Setting this bit to "1" forces a POR condition. This resets all internal registers to zero. Setting this bit to "1" disables the WKUP pin function. CAUTION: Setting this pin to `1' prevents a wake up condition. If the device then goes to sleep, it cannot be waken without a communication link that resets this bit, or by power cycling the device. Setting this bit to "1" sets the device to wake up on a rising edge at the WKUP pin. Setting this bit to "0" sets the device to wake up on a falling edge at the WKUP pin.
3
2 1
0
WKPOL Wake Up Polarity
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FN6446.1 November 2, 2007
ISL9208
.
TABLE 10. WRITE ENABLE REGISTER (ADDR: 08H) BIT 7 6 5 4 3 2 1 0 FUNCTION DESCRIPTION
FSETEN When set to "1", allows writes to the Feature Set register. When set to "0", prevents writes to the Feature Enable discharge set writes Set register (Addr: 07H). Default on initial power up is "0". CHSETEN Enable charge set writes When set to "1", allows writes to the Charge Set register. When set to "0", prevents writes to the Feature Set register (Addr: 06H). Default on initial power up is "0".
DISSETEN When set to "1", allows writes to the Discharge Set register (Addr: 05H). When set to "0", prevents writes Enable discharge set writes to the Feature Set register. Default on initial power up is "0". UFLG3 User Flag 3 UFLG2 User Flag 3 RESERVED RESERVED RESERVED General purpose flag usable by microcontroller software. This bit is battery backed up, even when RGO turns off. General purpose flag usable by microcontroller software. This bit is battery backed up, even when RGO turns off. Reserved for future expansion. Reserved for future expansion. Reserved for future expansion.
Device Description
Design Theory
Instructed by the microcontroller, the ISL9208 performs cell voltage monitoring and cell balancing operations, overcurrent and short circuit monitoring with automatic pack shutdown using built-in selectable time delays, and automatic turn off of the power FETs and cell balancing FETs in an over-temperature condition. All automatic functions of the ISL9208 can be turned off and the microcontroller can manage the operations through software.
System Power-Up/Power-Down
The ISL9208 powers up when the voltages on VCELL1, VCELL2, VCELL3, and VCC all exceed their POR threshold. At this time, the ISL9208 wakes up and turns on the RGO output. RGO provides a regulated 3.3VDC 10% voltage at pin RGO. It does this by using a control voltage on the RGC pin to drive an external NPN transistor (See Figure 2.) The transistor should have a beta of at least 70 to provide ample current to the device and external circuits and should have a VCE of greater than 30V (preferably 50V). The voltage at the emitter of the NPN transistor is monitored and regulated to 3.3V by the control signal RGC. RGO also powers most of the ISL9208 internal circuits. A 500 resistor is recommended in the collector of the NPN transistor to minimize initial current surge when the regulator turns on. Once powered up, the device remains in a wake up state until put to sleep by the microcontroller (typically when the cells drop too low in voltage) or until the VCELL1, VCELL2, VCELL3, or VCC voltages drop below their POR threshold.
Battery Connection
The ISL9208 supports packs of 5 to 7 series connected Li-ion cells. Connection guidelines for each cell combination are shown in Figure 1.
7 CELLS VCELL7 CB7 VCELL6 CB6 VCELL5 CB5 VCELL4 CB4 VCELL3 CB3 VCELL2 CB2 VCELL1 CB1 VSS 6 CELLS VCELL7 CB7 VCELL6 CB6 VCELL5 CB5 VCELL4 CB4 VCELL3 CB3 VCELL2 CB2 VCELL1 CB1 VSS 5 CELLS VCELL7 CB7 VCELL6 CB6 VCELL5 CB5 VCELL4 CB4 VCELL3 CB3 VCELL2 CB2 VCELL1 CB1 VSS
VCC
500
RGC
RGO VSS
3.3V
Note: Multiple cells can be connected in parallel
GND
FIGURE 1. BATTERY CONNECTION OPTIONS FIGURE 2. VOLTAGE REGULATOR CIRCUITS
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ISL9208
WKUP Pin Operation
There are two ways to design a wake up of the ISL9208. In an active LOW connection (WKPOL = "0" - default), the device wakes up when a charger is connected to the pack. This pulls the WKUP pin low when compared to a reference based on the VCELL1 voltage. In an active HIGH connection (WKPOL = `1') the device wakes up when the WKUP pin is pulled high by a connection through an external switch. In an overcurrent condition, the ISL9208 automatically turns off the voltage on CFET and DFET pins. The DFET output drives the discharge FET gate low, turning off the FET quickly. The CFET output turns off and allows the gate of the charge FET to be pulled low through a resistor. By turning off the FETs the ISL9208 prevents damage to the battery pack caused by excessive current into or out of to the cells (as in the case of a faulty charger or short circuit condition). When the ISL9208 detects a discharge overcurrent condition, both power FETs are turned off and the DOC bit is set. (When the FETs are turned off, the DFET and CFET bits are also reset.) The automatic response to overcurrent during discharge is prevented by setting the DENOCD bit to "1". The external microcontroller can turn on the FETs at any time to recover from this condition, but it would usually turn on the load monitor function (by setting the LDMONEN bit) and monitor the LDFAIL bit to detect that the overcurrent condition has been removed. When the ISL9208 detects a discharge short circuit condition, both power FETs are turned off and DSC bit is set. (When the FETs are turned off, the DFET and CFET bits are also reset.) The automatic response to short circuit during discharge is prevented by setting the DENSCD bit to "1". The external microcontroller can turn on the FETs at any time to recover from this condition, but it would usually turn on the load monitor function (by setting the LDMONEN bit) and monitor the LDFAIL bit to detect that the overcurrent condition has been removed. When the ISL9208 detects a charge overcurrent condition, both power FETs are turned off and COC bit is set. (When the FETs are turned off, the DFET and CFET bits are also reset.) The automatic response to overcurrent during discharge is prevented by setting the DENOCC bit to "1". The external microcontroller can turn on the FETs at any time to recover from this condition, but it would usually wait to do this until the cell voltages are not over charged and that the overcurrent condition has been removed. Or, the microcontroller could wait until the pack is removed from the charger and then re-attached. An alternative method of providing the protection function, if desired by the designer, is to turn off the automatic safety response. In this case, the ISL9208 devices still monitor the conditions and set the status bits, but take no action in overcurrent or short circuit conditions. Safety of the pack depends, instead, on the microcontroller to send commands to the ISL9208 to turn off the FETs. To facilitate a microcontroller response to an overcurrent condition, especially if the microcontroller is in a low power state, a charge overcurrent flag (COC), a discharge overcurrent flag (DOC), or the short circuit flag (DSC) being set causes the ISL9208 TEMP3V output to turn on and pull high. (See Figure 5.) This output can be used as an external interrupt by the microcontroller to wake-up quickly to handle the overcurrent condition.
FN6446.1 November 2, 2007
ISL9208 WKUP
WKUP (STATUS)
5V 230k*
WAKE UP CIRCUITS
WKPOL (CONTROL)
VCELL1
VSS
* Internal resistor only connected when WKPOL=1. FIGURE 3. WAKE UP CONTROL CIRCUITS
Protection Functions
In the default recommended condition, the ISL9208 automatically responds to discharge overcurrent, discharge short circuit, charge overcurrent, internal over-temperature, and external over-temperature conditions. The designer can set optional over-ride conditions that allow the response to be dictated by the microcontroller. These are discussed below. OVERCURRENT SAFETY FUNCTIONS The ISL9208 continually monitors the discharge current by monitoring the voltage at the CSENSE and DSENSE pins. If that voltage exceeds a selected value for a time exceeding a selected delay, then the device enters an overcurrent or short circuit protection mode. In these modes, the ISL9208 automatically turns off both power FETs and hence prevents current from flowing through the terminals P+ and P-. The voltage thresholds and the response times of the overcurrent protection circuits are selectable for discharge overcurrent, charge overcurrent, and discharge short circuit conditions. The specific settings are determined by bits in the Discharge Set Configuration Register (ADDR:05H) on page 15, and the Charge/Time Scale Configuration Scale Register (ADDR:06H) on page 16. In addition, refer to "Registers" on page 12.
18
ISL9208
P+ VSS OPEN
RL
combination of the load resistor, an external adjustment resistor (R1), and the internal load monitor resistor form a voltage divider. R1 is chosen so that when the load is released to a sufficient level, the LDFAIL condition is reset. OVER-TEMPERATURE SAFETY FUNCTIONS
POWER FETs R1 ISL9208 VMON
P-
External Temperature Monitoring The external temperature is monitored by using a voltage divider consisting of a fixed resistor and a thermistor. This divider is powered by the ISL9208 TEMP3V output. This output is normally controlled so it is on for only short periods to minimize current consumption. Without microcontroller intervention, and in the default state, the ISL9208 provides an automatic temperature scan. This scan circuit repeatedly turns on TEMP3V output (and the external temperature monitor) for 5ms out of every 640ms. In this way, the external temperature is monitored even if the microcontroller is asleep.
VREF LDFAIL = 1 if VMON >VVMONH = 0 if VMON VVMONL LDMONEN
VSS
FIGURE 4. LOAD MONITOR CIRCUIT
LOAD MONITORING The load monitor function in the ISL9208 (see Figure 4) is used primarily to detect that the load has been removed following an overcurrent or short circuit condition during discharge. This can be used in a control algorithm to prevent the FETs from turning on while the overload or short circuit condition remains. The load monitor can also be used by the microcontroller algorithms after an undervoltage condition on any cells causes the FETs to turn off. Use of the load monitor prevents the FETs from turning on while the load is still present. This minimizes the possible "oscillations" that can occur when a load is applied in a low capacity pack. It can also be part of a system protection mechanism to prevent the load from turning on automatically - i.e. some action must be taken before the pack is again turned on. The load monitor circuit can be turned on or off by the microcontroller. It is normally turned off to minimize current consumption. It must be activated by the external microcontroller for it to operate. The circuit works by internally connecting the VMON pin to VSS through a resistor. The circuit operates shown as in Figure 4. In a typical pack operation, when an overcurrent or short circuit event happens, the DFET turns off, opening the battery circuit to the load. At this time, the RL is small and the load monitor is initially off. In this condition, the voltage at VMON rises to nearly the pack voltage. Once the power FETs turn off, the microcontroller activates the load monitor by setting the LDMONEN bit. This turns on an internal FET that adds a pull down resistor to the load monitor circuit. While still in the overload condition the
When the TEMP3V output turns on, the ISL9208 waits 1ms for the temperature reading to stabilize, then compares the external temperature voltage with an internal voltage divider that is set to TEMP3V/13. When the thermistor voltage is below the reference threshold after the delay, an external temperature fail condition exists. To set the external overtemperature limit, set the value of RX resistor to the 12 times the resistance of the thermistor at the over-temp threshold. The TEMP3V output pin also turns on when the microcontroller sets the AO3:AO0 bits to select that the external temperature voltage. This causes the TEMPI voltage to be placed on AO and activates (after 1ms) the over-temperature detection. As long as the AO3:AO0 bits point to the external temperature, the TEMP3V output remains on. Because of the manual scan of the temperature, it may be desired to turn off the automatic scan, although they can be used at the same time without interference. To turn off the automatic scan, set the ATMPOFF bit. The microcontroller can over-ride both the automatic temperature scan and the microcontroller controlled temperature scan by setting the TEMP3ON configuration bit. This turns on the TEMP3V output to keep the temperature control voltage on all the time, for a continuous monitoring of an over-temperature condition. This likely will consume a significant amount of current, so this feature is usually used for special or test purposes. Protection As a default, when the ISL9208 detects an internal or external over-temperature condition, the FETs are turned off, the cell balancing function is disabled, and the IOT bit or XOT bit (respectively) is set.
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ISL9208
Turning off the FETs in the event of an over-temperature condition prevents continued discharge or charge of the cells when they are over heated. Turning off the cell balancing in the event of an over-temperature condition prevents damage to the IC in the event too many cells are being balanced, causing too much power dissipation in the ISL9208. In the event of an automatic over-temperature condition, cell balancing is prevented and FETs are held off until the temperature drops back below the temperature recovery threshold. During this temperature shutdown period, the microcontroller can monitor the internal temperature through the analog output pin (AO), but any writes to the CFET bit, DFET bit, or cell balancing bits are ignored The automatic response to an internal over-temperature is prevented by setting the DISITSD bit to "1". The automatic response to an external over-temperature is prevented by setting the DISXTSD bit to "1". In either case, it is important for the microcontroller to monitor the internal and external temperature to protect the pack and the electronics in an over-temperature condition.
4ms OVERCURRENT PROTECTION CIRCUITS I2C 508ms I2C OSC CHARGE OC DISCHARGE OC DISCHARGE SC
REGISTERS
ATMPOFF TMP3ON
RGO AO3:AO0 DECODE EXT TEMP TEMP3V 12R RX TEMPI TO C
VSS (ON) AO MUX 1ms DELAY EXTERNAL TEMP MONITOR
Analog Multiplexer Selection
The ISL9208 devices can be used to externally monitor individual battery cell voltages and temperatures. Each quantity can be monitored at the analog output pin (AO). The desired voltage is selected using the I2C interface and the AO3:AO0 bits. See Figure 6. VOLTAGE MONITORING Since the voltage on each of the Li-ion Cells are normally higher than the regulated supply voltage, and since the voltages on the upper cells is much higher than is tolerated by a microcontroller, it is necessary to both level shift and divide the voltage before it can be monitored by the microcontroller or an external A/D converter. To get into the voltage range required by the external circuits, the voltage level shifter divides the cell voltage by 2 and references it to VSS. Therefore, a Li-ion cell with a voltage of 4.2V becomes a voltage of 2.1V on the AO pin. TEMPERATURE MONITORING The voltage representing the external temperature applied at the TEMPI terminal is directed to the AO terminal through a MUX, as selected by the AO control bits (see Figures 5 and 6). The external temperature voltage is not divided by 2 as are the cell voltages. Instead it is a direct reflection of the voltage at the TEMPI pin. A similar operation occurs when monitoring the internal temperature through the AO output, except there is no external "calibration" of the voltage associated with the internal temperature. For the internal temperature monitoring, the voltage at the output is linear with respect to temperature. See "Operating Specifications" for information about the output voltage at +25C and the output slope relative to temperature on page 7.
AO
R
XOT TEMP FAIL INDICATOR
VSS
FIGURE 5. EXTERNAL TEMPERATURE MONITORING AND CONTROL
SCL SDA
I2C
LEVEL SHIFT LEVEL SHIFT
VC7/VCC
VCELL6
REGS AO3:AO0 DECODE LEVEL SHIFT LEVEL SHIFT VCELL2
2 MUX
VCELL1
VSS EXT TEMP. TEMPI MUX INT TEMP
FIGURE 6. ANALOG OUTPUT MONITORING DIAGRAM
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ISL9208
ISL9208
Cell Balancing
OVERVIEW A typical ISL9208 Li-ion battery pack consists of five to seven cells in series, with one or more cells in parallel. This combination gives both the voltage and power necessary for power tool, e-bikes, electric wheel chairs, portable medical equipment, and battery powered industrial applications. While the series/parallel combination of Li-ion cells is common, the configuration is not as efficient as it could be, because any capacity mismatch between series-connected cells reduces the overall pack capacity. This mismatch is greater as the number of series cells and the load current increase. Cell balancing techniques increase the capacity, and the operating time, of Li-ion battery packs. DEFINITION OF CELL BALANCING Cell balancing is defined as the application of differential currents to individual cells (or combinations of cells) in a series string. Normally, of course, cells in a series string receive identical currents. A battery pack requires additional components and circuitry to achieve cell balancing. For the ISL9208 devices, the only external components required are balancing resistors. CELL BALANCE OPERATION Cell balancing is accomplished through a microcontroller algorithm. This algorithm compares the cell voltages (a representation of the pack capacity) and turns on balancing for the cells that have the higher voltages. There are many parameters that should be considered when writing this algorithm. An example cell balancing algorithm is available in the ISL9208EVAL1Z evaluation kit. The microcontroller turns on the specific cell balancing by setting a bit in the Cell Balance Register. Each bit in the register corresponds to one cell's balancing control. When the bit is set, an internal cell balancing FET turns on. This shorts an external resistor across the specified cell. The maximum current that can be drawn from (or bypassed around) the cell is 200mA. This current is set by selecting the value of the external resistor. Figure 7 shows an example with a 200mA (maximum) balancing current. With lower balancing current, more balancing FETs can be turned on at once, without exceeding the device power dissipation limits or generating excessive balancing current that will heat the external resistor. differential between the minimum pack voltage and maximum charger voltage does not exceed 22V. When the pack is designed with a single set of charge/discharge FETs, the ISL9208 CFET pin should be protected in the event of an over-current or short circuit shutdown. When this happens, the FET opens suddenly. The flyback voltage from the motor windings could exceed the maximum input voltage on the CFET pin. So, it is recommended that an additional external series diode be placed between the CFET pin of the ISL9208 and the gate of the Charge FET. See Diode D3 in Figure 8. This will reduce the CFET gate voltage, but not significantly. Finally, to protect the Charge FET itself in the event of a large negative voltage on the Pack- pin, zener diode D4 is added. The large negative voltage can occur when the P- pin goes significantly negative, while the CFET pin is being internally clamped at VSS. The zener voltage of D4 should be less than the VGS(max) specification of the FET.
VC7/VCC 21 1W ISL9208 CB7
200mA CELL BALANCE CONTROL (REG 02H)
7654321 VCELL1 21 1W
CB1
VSS
FIGURE 7. CELL BALANCING CONTROL EXAMPLE WITH 200mA BALANCING CURRENT
PACK+
PACKD1 VMON 10M ISL9208 D3 CFET D4 1M
External VMON/CFET Protection Mechanisms
When there is a single charge/discharge path, a blocking diode is recommended in the VMON to P- path in ISL9208 solution. See D1 in Figure 8. This diode is to protect against a negative voltage on the VMON pin that can occur when the FETs are off and the charger connects to the pack. This diode is not needed when there is a separate charge and discharge path, because the voltages on P- (discharge) are likely always positive. The diode also is not needed if the 21
DFET
FIGURE 8. USE OF A DIODES FOR PROTECTING THE CFET AND VMON PINS
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ISL9208
User Flags
The ISL9208 contains four flags in the register area that the microcontroller can use for general purpose indicators. These bits are designated UFLG3, UFLG2, UFLG1, and UFLG0. The microcontroller can set or reset these bits by writing into the appropriate register. The user flag bits are battery backed up, so the contents remain even after exiting a sleep mode. However, if the microcontroller sets the POR bit to force a power on reset, all of the user flags will also be reset. In addition, if the voltage on cell1 ever drops below the POR voltage, the contents of the user flags (as well as all other register values) could be lost. The device responds with an acknowledge after recognition of a start condition and the correct slave byte. If a write operation is selected, the device responds with an acknowledge after the receipt of each subsequent eight bits. The device acknowledges all incoming data and address bytes, except for the slave byte when the contents do not match the device's internal slave address. In the read mode, the device transmits eight bits of data, releases the SDA line, then monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the device will continues to transmit data. The device terminates further data transmissions if an acknowledge is not detected. The master must then issue a stop condition to return the device to Standby mode and place the device into a known state
Serial Interface
INTERFACE CONVENTIONS The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is called the master and the device being controlled is called the slave. The master always initiates data transfers, and provides the clock for both transmit and receive operations. Therefore, the ISL9208 devices operate as slaves in all applications. When sending or receiving data, the convention is the most significant bit (MSB) is sent first. So, the first address bit sent is bit 7. CLOCK AND DATA Data states on the SDA line can change only while SCL is LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. See Figure 9. START CONDITION All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. See Figure 10. STOP CONDITION All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the Standby power mode after a read sequence. A stop condition is only issued after the transmitting device has released the bus. See Figure 10. ACKNOWLEDGE Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, releases the bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge that it received the eight bits of data. See Figure 11.
SCL
SDA DATA STABLE DATA CHANGE
DATA STABLE
FIGURE 9. VALID DATA CHANGES ON I2C BUS
.
SCL
SDA START
STOP
FIGURE 10. I2C START AND STOP BITS
SCL FROM MASTER
1
8
9
DATA OUTPUT FROM TRANSMITTER
DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE
FIGURE 11. ACKNOWLEDGE RESPONSE FROM RECEIVER
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ISL9208
WRITE OPERATIONS For a write operation, the device requires a slave byte and an address byte. The slave byte specifies the particular device on the I2C bus that the master is writing to. The address specifies one of the registers in that device. After receipt of each byte, the device responds with an acknowledge, and awaits the next eight bits from the master. After the acknowledge, following the transfer of data, the master terminates the transfer by generating a stop condition. See Figure 12. When receiving data from the master, the value in the data byte is transferred into the register specified by the address byte on the falling edge of the clock following the 8th data bit. After receiving the acknowledge after the data byte, the device automatically increments the address. So, before sending the stop bit, the master may send additional data to the device without re-sending the slave and address bytes. After writing to address 0AH, the address "wraps around" to address 0. Do not continue to write to addresses higher than address 08H, since these addresses access registers that are reserved. Writing to these locations can result in unexpected device operation.
SIGNALS FROM THE MASTER S T A R T S T O P
Read Operations
Read operations are initiated in the same manner as write operations with the host sending the address where the read is to start (but no data). Then, the host sends an ACK, a repeated start, and the slave byte with the LSB=1. After the device acknowledges the slave byte, the device sends out one bit of data for each master clock. After the slave sends eight bits to the master, the master sends a NACK (Not acknowledge) to the device, to indicate the data transfer is complete, then the master sends a stop bit. See Figure 13. After sending the eighth data bit to the master, the device automatically increments its internal address pointer. So the master, instead of sending a NACK and the stop bit, can send additional clocks to read the contents of the next register - without sending another slave and address byte. If the last address read or written is known, the master can initiate a current address read. In this case, only the slave byte is sent before data is returned. (See Figure 13.)
.
SLAVE BYTE
REGISTER ADDRESS
DATA
SDA BUS SIGNALS FROM THE SLAVE
01010000 A C K A C K A C K
ISL9208: SLAVE BYTE = 50H
FIGURE 12. WRITE SEQUENCE
Random Read
SIGNALS FROM THE MASTER S T A R T S T A R T N A C K S T O P S T A R T
Current Address Read
N A C K S T O P
SLAVE BYTE
REGISTER ADDRESS
SLAVE BYTE
SLAVE BYTE
SDA BUS SIGNALS FROM THE SLAVE
01010000 A C K A C K
01010001 A C K
01010001 A C K
DATA
DATA
ISL9208: SLAVE BYTE = 010100xH
FIGURE 13. READ SEQUENCE
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ISL9208
Register Protection
The Discharge Set, Charge Set, and Feature Set configuration registers are write protected on initial power up. In order to write to these registers it is necessary to set a bit to enable each one. These write enable bits are in the Write Enable register (Address 08H). Write the FSETEN bit (Addr 8:bit 7) to "1" to enable changes to the data in the Feature Set register (Address 7). Write the CHSETEN bit (Addr 8:bit 6) to "1" to enable changes to the data in the Feature Set register (Address 6).
POWER FAILS AND ONE OR MORE OF THE SUPPLIES, VCC, VCELL1, VCELL2, AND VCELL3 DO NOT MEET MINIMUM VOLTAGE REQUIREMENTS
Write the DISSETEN bit (Addr 8:bit 5) to "1" to enable changes to the data in the Feature Set register (Address 5). The microcontroller can reset these bits back to zero to prevent inadvertent writes that change the operation of the pack.
Operation State Machine
Figure 14 shows a device state machine which defines how the ISL9208 responds to various conditions.
POWER DOWN STATE
I2C INTERFACE IS DISABLED. BIASING IS DISABLED. ALL REGISTERS SET TO DEFAULT VALUES (ALL "0")
Power is applied and all of the supplies, VCC, VCELL1, VCELL2, and VCELL3 meet minimum voltage requirements POWER UP STATE
I2C INTERFACE IS ENABLED. BIASING IS ENABLED. VOLTAGE REGULATOR IS ENABLED.
MAIN OPERATING STATE
VOLTAGE REGULATOR IS ON LOGIC AND REGISTERS ARE POWERED BY RGO CFET, DFET, CELL BALANCING OUTPUTS ARE ALL OFF. (REQUIRE AN EXTERNAL COMMAND TO TURN ON) CHARGE AND DISCHARGE CURRENT PROTECTION CIRCUITS AND TEMPERATURE PROTECTION CIRCUITS ARE ACTIVE (DEFAULT). OVERCURRENT CONDITIONS FORCE POWER FETS TO TURN OFF. OVER-TEMPERATURE CONDITIONS FORCE POWER FETS AND CELL BALANCE OUTPUTS TO TURN OFF. VOLTAGE AND TEMPERATURE MONITORING CIRCUITS ARE AWAITING EXTERNAL CONTROL.
SLEEP STATE
VOLTAGE REGULATOR IS OFF BIASING IS OFF
SLEEP bit is set to `1'
LOGIC AND REGISTERS ARE POWERED BY VCELL1 CFET, DFET, CELL BALANCING OUTPUTS ARE ALL OFF.
WKUP goes above or below threshold (edge triggered). Or, SLEEP bit is set to `0'
CHARGE AND DISCHARGE CURRENT PROTECTION CIRCUITS ALL OFF. VOLTAGE AND TEMPERATURE MONITORING CIRCUITS ARE OFF. I2C COMMUNICATION IS ACTIVE (IF VCELL1 VOLTAGE IS HIGH ENOUGH TO OPERATE WITH THE EXTERNAL DEVICE.)
FIGURE 14. DEVICE OPERATION STATE MACHINE
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ISL9208
Applications Circuits
The following application circuits are ideas to consider when developing a battery pack implementation. There are many more ways that the pack can be designed. Also refer to the ISL9208, ISL9216, ISL9217 application guide for additional circuit design guidelines.
P+ ISL9208 0.1F VC7/VCC CB7 VCELL6 SCL CB6 VCELL5 CB5 VCELL4 CB4 VCELL3 THERM CB3 VCELL2 4.7F CB2 VCELL1 CB1 MINIMIZE LENGTH CSENSE MAXIMIZE GAUGE VSS DSREF AO VMON CFET DFET DSENSE SINGLE WIRE INTERFACE NOT NEEDED DURING DISCHARGE TEMP3V TEMPI RGC RGO 1F C VCC GP I/O SCL SDA INT A/D INPUT I/O
OPTIONAL LEDS RESISTORS
500
1.2M
10M
SDA WKUP
RESET
CHRG 100 3.6V
200k
16V (FIGURE 15. 7-CELL APPLICATION CIRCUIT INTEGRATED CHARGE/DISCHARGE
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ISL9208
ISL9208 0.1F VC7/VCC CB7 VCELL6 SCL CB6 VCELL5 CB5 VCELL4 CB4 VCELL3 THERM CB3 VCELL2 4.7F CB2 VCELL1 CB1 MINIMIZE LENGTH CSENSE DSENSE MAXIMIZE GAUGE DFET VSS DSREF AO VMON CFET TEMP3V TEMPI RGC RGO 1F C RESET GP I/O SCL SDA INT A/D INPUT I/O VCC SDA WKUP
500
1.2M
10M
OPTIONAL LEDS RESISTORS
CHRG 100 3.6V 200k
SINGLE WIRE INTERFACE NOT NEEDED DURING DISCHARGE OPTIONAL 16V CHG P-
OPTIONAL
B-
FIGURE 16. 7-CELL APPLICATION CIRCUIT SEPARATE CHARGE/DISCHARGE
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ISL9208
ISL9208 0.1F VC7/VCC CB7 VCELL6 SCL CB6 VCELL5 CB5 VCELL4 CB4 VCELL3 THERM CB3 VCELL2 4.7F CB2 VCELL1 CB1 MINIMIZE LENGTH CSENSE DSENSE MAXIMIZE GAUGE DFET VSS DSREF AO VMON CFET TEMP3V TEMPI RGC RGO 1F C RESET SDA WKUP
825k SW 500 TRIGGER IN ONE OF THESE LOCATIONS
10V
VCC GP I/O
OPTIONAL LEDS RESISTORS
SCL SDA INT A/D INPUT I/O
CHRG 100 3.6V SINGLE WIRE INTERFACE NOT NEEDED DURING DISCHARGE
OPTIONAL
16V
CHG P-
OPTIONAL
B-
FIGURE 17. 7-CELL APPLICATION CIRCUIT WITH SWITCH WAKE-UP AND SEPARATE CHARGE/DISCHARGE
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FN6446.1 November 2, 2007
ISL9208 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
L32.5x5B
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VHHD-2 ISSUE C MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L L1 N Nd Ne P 0.25 0.30 3.15 3.15 0.18 MIN 0.80 NOMINAL 0.90 0.20 REF 0.23 5.00 BSC 4.75 BSC 3.30 5.00 BSC 4.75 BSC 3.30 0.50 BSC 0.40 32 8 8 0.60 12 0.50 0.15 3.45 3.45 0.30 MAX 1.00 0.05 1.00 NOTES 9 9 5,8 9 7,8 9 7,8 8 10 2 3 3 9 9 Rev. 1 10/02 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 28
FN6446.1 November 2, 2007

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